This application is based upon and claims priority of Japanese Patent Application No 2001-090796, filed in Mar. 27, 2001, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a connection structure between an impurity-containing semiconductor layer and a conductive film and a method of manufacturing the same.
2. Description of the Prior Art
In recent years, the reduction of the consumption power of the semiconductor memory is required according to the increase of the use number of the mobile devices having the semiconductor memory.
The DRAM as one of the semiconductor memories has such a structure that the storage electrodes of the storage capacitor are connected to the impurity diffusion layers of the MOS transistor.
The charge (i.e. information) accumulated in the storage capacitor is reduced gradually by the leakage current from the storage node. Therefore, in order to maintain the accumulated charge at a predetermined value, the rewriting operation of the data in the storage capacitor is needed every predetermined period. This data rewriting operation is called the refresh operation.
If the period of the refresh operation is short, the consumption power of the DRAM is increased. Therefore, it is effective for the reduction in the consumption power to prolong the period of the refresh operation. For this reason, it is desired to improve the data holding characteristic (the refresh characteristic) of the storage node.
The refresh characteristic is limited by the junction leakage current that flows to the semiconductor substrate via the storage node of the memory cell. Various factors are expected as the causes to generate the junction leakage current, and thus it is not that such factors have already been clearly specified.
However, it is guessed that the generation of the junction leakage current is dominated by the crystal defects in the impurity diffusion layer, that are generated by the metallic contamination, the plasma exposure, etc. in the middle of the semiconductor device manufacturing steps.
For example, in the steps of forming the semiconductor element, the silicon substrate is exposed to the plasma several times in the etching steps to form the device isolation film, the sidewall, the bit line contact, the storage contact, etc.
Then, the step of forming the storage contact hole in the insulating film will be explained with reference to FIG. 1A hereunder.
In the situation that the MOS transistor 2 formed on the silicon substrate 1 is covered with the silicon oxide film 3, the first interlayer insulating film 4, and the second interlayer insulating film 5, the dry etching is applied to the silicon oxide film 3, the first interlayer insulating film 4, and the second interlayer insulating film 5 to form the contact hole 5a on one impurity diffusion layer 2a constituting the MOS transistor 2. The MOS transistor 2 is surrounded with the field oxide 8 formed on the silicon substrate 1. The dry etching is carried out via the window 6a of the resist pattern 6 formed on the second interlayer insulating film 5 until the first impurity diffusion layer 2a is exposed. Then, the storage electrode of the storage capacitor (not shown) formed on the second interlayer insulating film 5 is connected to the first impurity diffusion layer 2a via the contact hole 5a. 
In the etching to form the contact hole 5a, the first impurity diffusion layer 2a in the single crystal silicon substrate 1 is subjected to the ion impact of the plasma to cause the crystal defect. If the defect is caused in the first impurity diffusion layer 2a, the leakage of the accumulated charge occurs at the connecting portion (storage node) to the storage capacitor that is connected via the contact hole 5a, whereby the data holding characteristic (the refresh characteristic) of the storage capacitor is degraded.
In FIG. 1A, the MOS transistor 2 has the second impurity diffusion layer 2b that is formed adjacent to the first impurity diffusion layer 2a to put the channel region 2c between them, and the gate electrode 2e that is formed on the channel region 2c via the gate insulating film 2d. The bit line 7 on the first interlayer insulating film 4 is connected to the second impurity diffusion layer 2b via another contact hole 4a that is formed in the silicon oxide film 3 and the first interlayer insulating film 4.
In the meanwhile, in the step of etching the insulating film of the storage contact portion, in order to improve the selective etching ratio of the silicon oxide film 3 to the first impurity diffusion layer 2a, the pressure of the etching atmosphere is lowered and also the peak-to-peak voltage Vpp of the high frequency voltage applied to generate the ion is increased. However, if the voltage Vpp is increased, the ion energy is increased to cause the crystal defect of the first impurity diffusion layer 2a in the silicon substrate 1.
In contrast, if the voltage Vpp is reduced, the selective etching ratio of the silicon oxide film 3 to the first impurity diffusion layer 2a is lowered. Then, as shown in FIG. 1B, the first impurity diffusion layer 2a is dug to cause the storage contact failure.
Accordingly, as the method of reducing the degradation of the refresh characteristic, the method of lowering the voltage Vpp is not employed, but the method of avoiding the contact between the semiconductor substrate 1 and the metal atoms by clearing the manufacturing environment, in particular, removing the metallic contamination in the equipment is employed. However, such method is insufficient to further improve the refresh characteristic.
It is an object of the present invention to provide a semiconductor device capable of suppressing a leakage current generated at a contact portion between an impurity diffusion layer and a conductive film, and a method of manufacturing the same.
According to the present invention, since the metal element such as titanium is introduced into the impurity diffusion layer of the semiconductor substrate, the leakage of the charges caused at the connecting portion between the impurity diffusion layer and the overlying conductive plug is reduced. The metal element is titanium, nickel, cobalt, or platinum whose siliciding activation energy is less than 1.8 eV.
For example, it is experimentally checked that, if the metal element such as titanium ion, etc. is introduced into the impurity diffusion layer from the plasma containing ion of the metal element, the crystal defect of the semiconductor (silicon) substrate caused by ion impact of the plasma employed in the etching is compensated and also the refresh characteristic of the DRAM memory cell is improved.
Accordingly, the crystal defect in the semiconductor single crystal is reduced not to lower the selective etching ratio of the insulating film to the impurity diffusion layer in the semiconductor substrate. As a result, the generation of the leakage current from the contact portion between the impurity diffusion layer and the conductive film is relaxed, and also the refresh characteristic is improved in the memory cell.
For example, in the step of exposing the semiconductor substrate to the plasma by etching the insulating film on the semiconductor substrate, the titanium ion is positively introduced into the semiconductor substrate. According to this process, the crystal defect of the semiconductor substrate by the etching can be reduced and also the leakage current from the storage node can be reduced. Then, the DRAM having the memory cell that is excellent in the refresh characteristic is formed.
The titanium can be injected into the impurity diffusion layer by utilizing the over-etching in the insulating film etching step to form the storage contacts. Therefore, the refresh characteristic improving effect can be achieved not to require the addition of the special equipment and steps.